The Network Interface Card (NIC) is a logical place to start processing packets, since it is the first device that sees them. Traditionally, this has meant packet fragmentation and verifying checksums, but with the newest generation of NICs with built-in FPGAs it is possible to do much more.
In this meetup, Laddan Hashemian and Daniel Stackenas from Intel will share the latest news from Intel programmable NICS. They will give two presentations:
1) 30 min on: The Acceleration Stack for Intel(r) Xeon(r) CPU with FPGAs allows software developers to leverage the power of FPGAs much more easily than before. A core component is the FPGA Interface Manager, which provides performance-optimized connectivity between an Intel FPGA and an Intel Xeon processor. The FPGA can be directly transacted on with the Intel Acceleration Engine with OPAE Technology, which provides thread-safe application programming interfaces (APIs) that can be called from within virtual machines and containers. This relieves developers of crafting customized drivers and debugging interfaces, enabling them to focus on their core expertise - algorithm development - and develop their solutions faster and with greater confidence using OpenCL or traditional HDL design flow.
2) 30 min on: Orchestration and lifetime management of FPGA and other Intel technology using Cyborg provides the ability to manage accelerators in an OpenStack framework